View ADIS1622009_5048033.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Programmable Digital Vibration Sensor ADIS16220
FEATURES
Digital 70 g accelerometer/vibration sensing 22 kHz sensor resonance 100.2 kSPS sample rate SPI-compatible serial interface Programmable data capture function: 3 channels, 1024 samples each 1 accelerometer/2 auxiliary ADCs (AIN1, AIN2) Manual trigger for user initiation Automatic trigger for periodic data capture Event trigger for condition-driven capture Digital temperature sensor output Digitally controlled sample rate Digitally controlled frequency response 2 auxiliary digital I/Os Digitally activated self-test Digitally activated low power mode Serial number and device ID Single-supply operation: 3.15 V to 3.6 V Operating temperature range: -40C to +125C 9.2 mm x 9.2 mm 16-terminal LGA
GENERAL DESCRIPTION
The ADIS16220 iSensor(R) is a digital vibration sensor that combines industry-leading iMEMS(R) sensing technology with signal processing, data capture, and a convenient serial peripheral interface (SPI). The SPI and data buffer structure provide convenient access to wide-bandwidth sensor data. The 22 kHz sensor resonance and 100.2 kSPS sample rate provide adequate response for most machine-health applications. The averaging/ decimating filter provides optimization controls for lower bandwidth applications. An internal clock drives the data sampling system, which fills the buffer memory for user access. The data capture function has three different trigger modes. The automatic data collection allows for periodic wake-up and capture, based on a programmable duty cycle. The manual data capture mode allows the user to initiate a data capture, providing power and read-rate optimization. The event capture mode continuously updates the buffers and monitors them for a preset trigger condition. This mode captures pre-event data and post-event data and produces an alarm indicator for driving an interrupt. The ADIS16220 also offers a digital temperature sensor, digital power supply measurements, and peak output capture. The ADIS16220 comes in a 9.2 mm x 9.2 mm x 3.9 mm LGA package that meets the Pb-free solder reflow profile requirements per JEDEC J-STD-020 and has an extended operating temperature range of -40C to +125C.
APPLICATIONS
Vibration analysis Shock detection and event capture Condition monitoring Machine health Instrumentation, diagnostics Safety, shut-off sensing Security sensing, tamper detection
FUNCTION BLOCK DIAGRAM
DIO1 DIO2 RST VDD POWER MANAGEMENT
SELF-TEST
I/O
ALARMS
GND
MEMS SENSOR CONTROLLER TEMP SENSOR AIN1 AIN2 CLOCK FILTER
USER CONTROL REGISTERS SPI PORT OUTPUT DATA REGISTERS
CS SCLK DIN DOUT
CAPTURE BUFFER
VREF
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2009 Analog Devices, Inc. All rights reserved.
07980-001
ADIS16220
ADIS16220 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Function Block Diagram ................................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Specifications .................................................................. 5 Timing Diagrams.......................................................................... 5 Absolute Maximum Ratings............................................................ 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Recommended Pad Layout ......................................................... 7 Theory of Operation ........................................................................ 8 Sensing Element ........................................................................... 8 Data Sampling and Processing ................................................... 8 User Interface ................................................................................ 8 Basic Operation................................................................................. 9 SPI Write Commands .................................................................. 9 SPI Read Commands ....................................................................9 Data Collection ........................................................................... 11 Reading Data from the Capture Buffer ................................... 11 Capture Mode Configuration ................................................... 12 Global Commands ..................................................................... 13 Filtering........................................................................................ 13 Offset Adjustment ...................................................................... 14 Input/Output Functions ............................................................ 14 Diagnostics .................................................................................. 14 Serialization................................................................................. 15 Flash Memory Management ..................................................... 15 Applications Information .............................................................. 16 Assembly...................................................................................... 16 Getting Started Quickly ............................................................. 16 Interface Board ........................................................................... 16 Outline Dimensions ....................................................................... 17 Ordering Guide .......................................................................... 17
REVISION HISTORY
12/09--Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADIS16220 SPECIFICATIONS
TA = -40C to +125C, VDD = 3.3 V, 1 g, unless otherwise noted. Table 1.
Parameter ACCELEROMETER Measurement Range Sensitivity Sensitivity Error Sensitivity Temperature Coefficient Nonlinearity Cross-Axis Sensitivity Alignment Error Offset Error Offset Temperature Coefficient Output Noise Output Noise Density Sensor Resonant Frequency Self-Test Response AUXILIARY INPUTS (AIN1, AIN2) Resolution1 Sensitivity Integral Nonlinearity Differential Nonlinearity Offset Offset Error Input Range Input Capacitance ON-CHIP VOLTAGE REFEERENCE Output Level Accuracy Temperature Coefficient Output Impedance LOGIC INPUTS2 Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL All Except RST RST Input Capacitance, CIN DIGITAL OUTPUTS2 Output High Voltage, VOH Output Low Voltage, VOL FLASH MEMORY Endurance3 Data Retention4 START-UP TIME5 Initial Startup Reset Recovery (RST) Sleep Mode Recovery Conditions TA = 25C TA = 25C TA = 25C With respect to full scale With respect to package TA = 25C TA = 25C, AVG_CNT = 0x0000 TA = 25C, 10 Hz to 1 kHz 917 Min -70 19.073 5 310 0.2 2 1 -19.1 5 507 4 22 1310 12 305.18 2.4 4 VDD/2 20.4 0 20 2.5 5 40 70 2.0 VIH = 3.3 V VIL = 0 V 0.2 -40 -1 10 ISOURCE = 1.6 mA ISINK = 1.6 mA 2.4 0.4 10,000 20 160 23 2.3 0.8 1 -60 VDD Typ Max +70 Unit g mg/LSB % ppm/C % % Degree g mg/C mg rms mg/Hz kHz LSB Bits V/LSB LSB LSB V LSB V pF V mV ppm/C V V A A mA pF V V Cycles Years ms ms ms
2
+19.1
1703
TJ = 85C
RST or software (GLOB_CMD)
Rev. 0 | Page 3 of 20
ADIS16220
Parameter CONVERSION RATE Clock Accuracy POWER SUPPLY Power Supply Current Conditions AVG_CNT = 0x0000 Operating voltage range, VDD Capture mode, TA = 25C Sleep mode, TA = 25C Sleep mode, TA = 85C Sleep mode, TA = 125C Min Typ 100.2 3 3.3 38 230 250 600 Max Unit kSPS % V mA A A A
3.15
3.6 46
1 2
A 12-bit analog-to-digital converter is used to create a 14-bit digital scale for the AIN1 and AIN2 inputs. The digital I/O signals are 5 V tolerant. 3 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at -40C, +25C, +85C, and +125C. 4 Retention lifetime equivalent at junction temperature (TJ) = 85C as per JEDEC Standard 22, Method A117. Retention lifetime decreases with junction temperature. See Figure 16. 5 The start-up times presented do not include the data capture time, which is dependent on the AVG_CNT register settings.
Rev. 0 | Page 4 of 20
ADIS16220
TIMING SPECIFICATIONS
TA = 25C, VDD = 3.3 V, unless otherwise noted. Table 2.
Parameter fSCLK tSTALL tCS tDAV tDSU tDHD tSCLKR, tSCLKF tSR tSF tDF, tDR tSFS
1
Description SCLK frequency Stall period between data, between 16th and 17th SCLK Chip select to SCLK edge DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge SCLK rise/fall times SCLK high pulse width SCLK low pulse width DOUT rise/fall times CS high after SCLK edge
Min1 0.01 15.4 48.8 24.4 48.8
Typ
Max 2.25
100
5
5 5
12.5 12.5 12.5 12.5
Unit MHz s ns ns ns ns ns ns ns ns ns
Guaranteed by design, not tested.
TIMING DIAGRAMS
CS
tSR tSF tCS
1 2 3 4 5 6 15 16
tSFS
SCLK
tDAV
DOUT MSB DB14 DB13 DB12 DB11 DB10 DB2 DB1 LSB
tDSU
DIN R/W A6 A5
tDHD
A4 A3 A2 D2 D1 LSB
07980-002
Figure 2. SPI Timing and Sequence
tSTALL
CS
07980-003
SCLK
Figure 3. DIN Bit Sequence
Rev. 0 | Page 5 of 20
ADIS16220 ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Analog Inputs to GND Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g -0.3 V to +6.0 V -0.3 V to +5.3 V -0.3 V to VDD + 0.3 V -0.3 V to +3.6 V -40C to +125C -65C to +125C
Table 4. Package Characteristics
Package Type 16-Terminal LGA JA 250C/W JC 25C/W Device Weight 0.6 g
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 6 of 20
ADIS16220 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VREF AIN1 GND
16 15 14 13
VDD
12
SCLK
AIN2
1
PIN 1 INDICATOR
11 10 9
DOUT
ADIS16220
TOP LOOK THROUGH VIEW (Not to Scale)
NC
3
2
DIN
NC
CS
4
RST
A
5 6 7 8
DIO1
DIO2
Figure 4. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7, 8, 10, 11 9 12 13 14 15 16
1 2
Mnemonic SCLK DOUT DIN CS DIO1 DIO2 NC RST AIN2 VDD AIN1 VREF GND
Type1 I O2 I I I/O I/O N/A I I S I O S
Description SPI, Serial Clock. SPI, Data Output. SPI, Data Input. SPI, Chip Select. Digital Input/Output. Digital Input/Output. No Connect. Reset, Active Low. Analog Input Channel 2. Power Supply, 3.3 V. Analog Input Channel 1. Voltage Reference for AIN1 and AIN2. Ground.
S = supply; O = output; I = input; I/O = input/output. DOUT is an output when CS is low. When CS is high, DOUT is in a three-state, high impedance mode.
RECOMMENDED PAD LAYOUT
2.6955 8x 4.1865 8x
0.670 12x 8.373 2x 5.391 4x
0.500 16x
07980-006
1.127 16x 9.2mm x 9.2mm STACKED LGA PACKAGE
Figure 5. Recommended of a Pad Layout
Rev. 0 | Page 7 of 20
07980-005
NOTES 1. NC = NO CONNECT. 2. THIS IS NOT AN ACTUAL TOP VIEW, BECAUSE THE PINS ARE NOT VISIBLE FROM THE TOP. THIS IS A LAYOUT VIEW THAT REPRESENTS THE PIN CONFIGURATION IF THE PACKAGE IS LOOKED THROUGH FROM THE TOP. THIS CONFIGURATION IS PROVIDED FOR PCB LAYOUT PURPOSES.
NC
NC
ADIS16220 THEORY OF OPERATION
SPI PORT SPI PORT SPI SIGNALS
07980-007
The ADIS16220 is a wide-bandwidth, digital acceleration sensor for vibration analysis. This sensing system collects data autonomously and makes it available to any processor system that supports a 4-wire serial peripheral interface (SPI).
MEMS SENSOR
CAPTURE BUFFER OUTPUT REGISTERS
SENSING ELEMENT
Digital vibration sensing in the ADIS16220 starts with a widebandwidth MEMS accelerometer core that provides a linear motion-to-electrical transducer function. Figure 6 provides a basic physical diagram of the sensing element and its response to linear acceleration. It uses a fixed frame and a moving frame to form a differential capacitance network that responds to linear acceleration. Tiny springs tether the moving frame to the fixed frame and govern the relationship between acceleration and physical displacement. A modulation signal on the moving plate feeds through each capacitive path into the fixed frame plates and into a demodulation circuit, which produces the electrical signal that is proportional to the acceleration acting on the device.
ANCHOR
TEMP SENSOR
ADC CONTROLLER CONTROL REGISTERS
AIN SIGNALS CLOCK
Figure 7. Simplified Sensor Signal Processing Diagram
USER INTERFACE
SPI Interface
The user registers control operation and manage user access to both sensor data and configuration inputs. Each 16-bit register has its own unique bit assignment and has two addresses: one for its upper byte and one for its lower byte. Table 8 provides a memory map for each register, along with their function and lower byte address. Each data collection and configuration commands both use the SPI, which consists of four wires. The chip select (CS) signal activates the SPI interface and the serial clock (SCLK) synchronizes the serial data lines. Input commands clock into the DIN pin, one bit at a time, on the SCLK rising edge, and output data clocks out of the DOUT pin on the SCLK falling edge. As a SPI slave device, the DOUT contents reflect the information requested using a DIN command.
PLATE CAPACITORS
MOVABLE FRAME
ACCELERATION
FIXED PLATES UNIT SENSING CELL MOVING PLATE UNIT FORCING CELL
Dual Memory Structure
The user registers provide addressing for all input/output operations on the SPI interface. The control registers use a dual memory structure. The SRAM controls operation while the part is on, and facilitates all user configuration inputs. The flash memory provides nonvolatile storage for control registers that have flash backup (see Table 8). Storing configuration data in the flash memory requires a manual, flash update command (GLOB_ CMD[12] = 1, DIN = 0xBF10). When the device powers on or resets, the flash memory contents load into the SRAM, and then the device starts producing data according to the configuration in the control registers.
MANUAL FLASH BACKUP NONVOLATILE FLASH MEMORY (NO SPI ACCESS) START-UP RESET VOLATILE SRAM SPI ACCESS
07980-109
ANCHOR
Figure 6. MEMS Sensor Diagram
DATA SAMPLING AND PROCESSING
The analog acceleration signal feeds into an analog-to-digital (ADC) converter stage, which passes digitized data into the controller. The controller processes the acceleration data, stores it in the capture buffer, and manages access to it using the SPI/register user interface. Processing options include offset adjustment, filtering, and checking for preset alarm conditions.
07980-004
Figure 8. SRAM and Flash Memory Diagram
Rev. 0 | Page 8 of 20
ADIS16220 BASIC OPERATION
The ADIS16220 uses a serial peripheral interface (SPI) for communication, which enables a simple connection with a compatible, embedded processor platform, as shown in Figure 9. The two general-purpose lines provide options for a busy indicator, an alarm indicator, a general-purpose input/output function, and an external capture trigger input.
VDD VDD
13
UPPER BYTE
LOWER BYTE
Figure 10. Generic Register Bit Definitions
SPI WRITE COMMANDS
The control registers in Table 8 provide configuration options for a variety of functions. A master processor writes to the registers, one byte at a time, using simple firmware commands and the bit assignments in Figure 13. Because each byte in a register is independent, some functions only require one write cycle. For example, set GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a manual capture sequence. The manual capture starts immediately after the last bit clocks into DIN (16th SCLK rising edge).
CS SCLK
SYSTEM PROCESSOR SPI MASTER SS SCLK MOSI MISO IRQ1 IRQ2
4 1 3 2 5 6
ADIS16220
SPI SLAVE CS SCLK DIN DOUT DIO1 DIO2
07980-010
16
DIN
Figure 11. SPI Sequence for Manual Capture Start (DIN = 0xBF08)
Figure 9. Electrical Hook-Up Diagram
SPI READ COMMANDS
A single register read requires two 16-bit SPI cycles, which also use the bit assignments in Figure 13. The first sequence sets R/W = 0 and communicates the target address (A6:A0). For a read request, D7:D0 are don't care bits. For simplicity, set D7:D0 equal to zero during read request commands. DOUT clocks out during the second sequence. The second sequence can also use DIN to setup the next read. Figure 12 provides a signal diagram for all four SPI signals while reading the acceleration capture buffer (CAPT_BUFA) in a repeating pattern. In this diagram, DIN = 0x1400 and DOUT reflects the CAPT_BUFA register contents.
CS SCLK DIN DOUT DOUT = 1111 1001 1101 1010 = 0xF9DA = -1573 LSBs -30.002g DIN = 0001 0100 0000 0000 = 0x1400
Table 6. Generic Master Processor Pin Names and Functions
Pin Name SS IRQ1, IRQ2 MOSI MISO SCLK Function Slave select Interrupt request inputs Master output, slave input Master input, slave output Serial clock
The ADIS16220 SPI interface supports full duplex serial communication (simultaneous transmit and receive) and uses the bit sequence shown in Figure 13. Table 7 provides a list of the most common settings that require attention to initialize a processor's serial port for the ADIS16220 SPI interface. Table 7. Generic Master Processor SPI Settings
Processor Setting Master SCLK Rate 2.25 MHz SPI Mode 3 (1, 1) MSB-First 16-Bit Description ADIS16220 operates as a slave Bit rate setting Clock polarity/phase (CPOL = 1, CPHA = 1) Bit sequence Shift register/data length
Figure 12. Example SPI Read, Second 16-Bit Sequence
The user registers in Table 8 govern all data collection and configuration. Figure 10 provides a generic bit assignment when referencing each registers' bit descriptions.
CS SCLK DIN DOUT R/W DB15 A6 A5 A4 A3 A2 A1 A0 DB8 D7 DB7 D6 DB6 D5 DB5 D4 DB4 D3 DB3 D2 DB2 D1 DB1 D0 DB0 R/W DB15 A6 A5
DB14 DB13 DB12 DB11 DB10 DB9
DB14 DB13
07980-111
NOTES 1. DOUT BITS ARE BASED ON THE PREVIOUS 16-BIT SEQUENCE (R/W = 0).
Figure 13. Example SPI Read Sequence
Rev. 0 | Page 9 of 20
07980-212
07980-112
07980-110
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ADIS16220
Note that all registers in Table 8 consist of two bytes. All unused memory locations are reserved for future use. Table 8. User Register Memory Map
Name FLASH_CNT ACCL_NULL AIN1_NULL AIN2_NULL CAPT_SUPPLY CAPT_TEMP CAPT_PEAKA CAPT_PEAK1 CAPT_PEAK2 CAPT_BUFA CAPT_BUF1 CAPT_BUF2 CAPT_PNTR CAPT_CTRL CAPT_PRD ALM_MAGA ALM_MAG1 ALM_MAG2 ALM_MAGS ALM_CTRL GPIO_CTRL MSC_CTRL DIO_CTRL AVG_CNT DIAG_STAT GLOB_CMD ST_DELTA LOT_ID1 LOT_ID2 PROD_ID SERIAL_NUM
1
Access Read only Read/write Read/write Read/write Read only Read only Read only Read only Read only Read only Read only Read only Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read/write Read only Write only Read only Read only Read only Read only Read only
Flash Backup Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No Yes Yes Yes Yes Yes
Address1 0x00 0x02 0x04 0x06 0x08 to 0x09 0x0A 0x0C 0x0E 0x10 0x12 0x14 0x16 0x18 0x1A 0x1C 0x1E 0x20 0x22 0x24 0x26 0x28 0x2A to 0x31 0x32 0x34 0x36 0x38 0x3A to 0x3B 0x3C 0x3E 0x40 0x42 to 0x51 0x52 0x54 0x56 0x58
Default N/A 0x0000 0x0000 0x0000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x0000 0x0020 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0003 0x000F 0x0000 0x0000 N/A N/A N/A N/A 0x3F5C N/A
Function Status, flash memory write count Control, acceleration offset adjustment control Control, AIN1 offset adjustment control Control, AIN2 offset adjustment control Reserved Output, power supply during capture Output, temperature during capture Output, peak acceleration during capture Output, peak AIN1 level during capture Output, peak AIN2 level during capture Output, capture buffer for acceleration Output, capture buffer for AIN1 Output, capture buffer for AIN2 Control, capture buffer address pointer Control, capture control register Control, capture period (automatic mode) Control, Alarm A, acceleration peak threshold Control, Alarm 1, AIN1 peak threshold Control, Alarm 2, AIN2 peak threshold Control, Alarm S, peak threshold Control, alarm configuration register Reserved Control, general I/O configuration Control, self-test control, AIN configuration Control, digital I/O configuration Control, filter configuration Reserved Status, system status Control, system commands Status, self-test response Reserved Date code identification Date code identification Product identifier; convert to decimal = 16220 Serial number
Bit Assignments Table 35 Table 25 Table 26 Table 26 Table 10 Table 10 Table 10 Table 10 Table 10 Table 10 Table 10 Table 10 Table 9 Table 15 Table 16 Table 19 Table 20 Table 20 Table 21 Table 18 Table 28 Table 30 Table 27 Table 24 Table 29 Table 23 Table 31 Table 32 Table 33 N/A Table 34
Each register contains two bytes. The address of the lower byte is displayed. The address of the upper byte is equal to the address of the lower byte, plus 1.
Rev. 0 | Page 10 of 20
ADIS16220
DATA COLLECTION
The ADIS16220 samples and stores acceleration (vibration) and analog input signal data using capture events. A capture event involves several sampling/processing operations, as shown in Figure 14. First, the ADIS16220 produces and stores 1024 samples of acceleration and analog input channel data into the capture buffers. Second, the capture event takes a 5.12 ms record of power supply measurements at a sample rate of 50 kHz and loads the average of this record into the CAPT_ SUPPLY register. Third, the capture event takes 64 samples of internal temperature data over a period of 1.7 ms and loads the average of this record into CAPT_TEMP.
DATA IN BUFFERS LOAD INTO USER OUTPUT REGISTERS CAPT_BUF2
Table 10. Capture Output Register Formats
Register CAPT_SUPPLY CAPT_TEMP CAPT_BUFA, CAPT_PEAKA CAPT_BUF1, CAPT_BUF2, CAPT_PEAK1, CAPT_PEAK2
1
Format1 12-bit binary, 0 V = 0 LSB, 1.2207 mV/LSB 12-bit binary, +25C = 1278 LSB, -0.47C/LSB 16-bit twos complement 19.073 mg/LSB 16-bit twos complement 305.18 V/LSB
Reference Table 13 Table 14 Table 11 Table 12
12-bit data formats are LSB justified. Upper four bits are not used in these cases.
Table 11. CAPT_BUFA1 Data Format Examples
Acceleration (g) +70 +0.019073 0 -0.019073 -70
1
CAPT_BUF1 0 CAPT_BUFA CAPT_PNTR AIN2 CAPTURE BUFFER 1023 AIN1 CAPTURE BUFFER ACCELEROMETER CAPTURE BUFFER TRIPLE-CHANNEL CAPTURE BUFFER 1024 SAMPLES EACH 16-BIT DATA
LSB +3670 +1 0 -1 -3670
Hex 0x0E56 0x0001 0x0000 0xFFFF 0xF1AA
Output (Binary) 0000 1110 0101 0111 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 0001 1010 1010
This table also applies to the CAPT_PEAKA register.
Table 12. CAPT_BUF11 Data Format Examples
CAPT_SUPPLY
INTERNAL SAMPLING SYSTEM FILLS THE CAPTURE BUFFER AND OUTPUT REGISTERS
CAPT_TEMP
Figure 14. Acceleration Capture Buffer Structure and Operation; CAPT_BUF1 (AIN1) and CAPT_BUF2 (AIN2) Use Similar Structures
READING DATA FROM THE CAPTURE BUFFER
When a capture is complete, the first data samples load into the CAPT_BUFx registers and 0x0000 loads into the index pointer (CAPT_PNTR). The index pointer determines which data samples load into the CAPT_BUFx registers. For example, writing 0x0138 to the CAPT_PNTR register (DIN = 0x9A38, DIN = 0x9B01) causes the 313th sample in the buffer memory to load into the CAPT_BUFx registers. Table 9. CAPT_PNTR Bits Descriptions
Bit [15:10] [9:0] Description (Default = 0x0000) Reserved Data bits
Level (mV)2 VDD/2+1000 VDD/2+0.305 VDD/2 VDD/2-0.305 VDD/2-1000
1
LSB +3277 +1 0 -1 -3277
Hex 0x0CCD 0x0001 0x0000 0xFFFF 0xF333
Output (Binary) 0000 1100 1100 1101 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 0011 0011 0011
07980-014
2
This table also applies to CAPT_BUF2, CAPT_PEAK1, and CAPT_PEAK2 registers. This applies for MSC_CTRL = 0x0003. When MSC_CTRL = 0x0000, substitute 3300 mV for VDD.
Table 13. CAPT_SUPPLY Data Format Examples
Supply Level (V) 3.6 3.3 + 0.0012207 3.3 3.3 - 0.0012207 3.15 LSB 2949 2704 2703 2702 2580 Hex 0xB85 0xA90 0xA8F 0xA8E 0xA14 Binary Output 1011 1000 0101 1010 1001 0000 1010 1000 1111 1010 1000 1110 1010 0001 0100
Table 14. CAPT_TEMP Data Format Examples
Temperature (C) +125 +25.47 +25 +24.53 -40 LSB 1065 1277 1278 1279 1416 Hex 0x429 0x4FD 0x4FE 0x4FF 0x588 Binary Output 0100 0100 1001 0100 1111 1101 0100 1111 1110 0100 1111 1111 0101 1000 1000
The index pointer automatically increments with a CAPT_BUFA, CAPT_BUF1, or CAPT_BUF2 read command, which causes the next set of capture data to load into each capture buffer register.
Output Data Format
Table 10 offers a summary of the data format used by each output registers. Table 11, Table 12, Table 13, and Table 14 provide example output coding for each register.
Rev. 0 | Page 11 of 20
ADIS16220
CAPTURE MODE CONFIGURATION
The CAPT_CTRL register (see Table 15) offers three modes of capture operation (manual, automatic, and event), along with a number of configuration features for supporting these modes. All three modes use the start/stop bit, located in GLOB_ CMD[11] (see Table 23) to manage the capture operation. Table 15. CAPT_CTRL Bit Descriptions
Bit [15:7] [6] [5:4] Description (Default = 0x0020) Reserved Automatically store capture buffers to flash upon alarm trigger (1 = enabled) Pre-event capture length for event mode 00 = 64 samples 01 = 128 samples 10 = 256 samples 11 = 512 samples Capture mode 00 = manual: use GLOB_CMD[11] to start capture 01 = automatic: use CAPT_PRD[9:0] to set capture period 10 = event: continuously monitor data for the conditions set in ALM_CTRL, ALM_MAGA, ALM_MAG1, and ALM_MAG2. 11 = not used Power-down between capture events 1 = enabled, which requires CS toggle to wake up Reserved
Table 17. Example Automatic Mode Configuration Sequence
DIN 0x9F02, 0x9E18 0x9C06 0xBF08 Description CAPT_PRD[15:8] = 0x02, set time scale to hours CAPT_PRD[7:0] = 0x18, set the capture period to 24 hours Set the device for trigger mode and enable shutdown Start: device executes a capture and shuts down
Event Capture Mode
The event mode functions in a manner similar to a single-event trigger on a digital oscilloscope. This mode is useful for capturing shock events and for preshock motion/vibration analysis. Once started, it monitors a continuous stream of real-time data for a preset, event trigger condition. The event trigger settings are in the following registers: ALM_CTRL (see Table 18), ALM_MAGA (see Table 19), and ALM_MAG1/ALM_MAG2 (see Table 20). When the acceleration or analog input signals trip the alarm trigger settings, the device fills the capture buffers with pretrigger and post-trigger data, according to the pre-trigger configuration in CAPT_CTRL[5:4]. Configuring the device in the event capture mode requires four steps: 1. 2. 3. 4. Select which data channels to enable using ALM_CTRL. Set each threshold using the ALM_MAGx registers. Select event capture mode by setting CAPT_CTRL[3:2] = 10. Start the sampling by setting GLOB_CMD[11] = 1. Table 22 provides an example for configuring the device in this mode. After the continuously sampling starts, setting GLOB_CMD[11] = 1 stops the sampling process.
Description (Default = 0x0000) Reserved System alarm comparison polarity 1 = trigger when less than ALM_MAGS[11:0] 0 = trigger when greater than ALM_MAGS[11:0] System alarm trigger source 1 = temperature, 0 = power supply System alarm enable (ALM_MAGS) 1 = enabled, 0 = disabled AIN2 alarm enable (ALM_MAG2) 1 = enabled, 0 = disabled AIN1 alarm enable (ALM_MAG1) 1 = enabled, 0 = disabled Acceleration alarm enable (ALM_MAGA) 1 = enabled, 0 = disabled
[3:2]
[1] [0]
Manual Capture Mode
The factory default configuration for capture mode is the manual mode. In the manual mode, the ADIS16220 waits for a start command to execute the capture event. Set GLOB_CMD[11] = 1 (DIN = 0xBF08) to start a capture in this mode. Once the capture process begins, GLOB_CMD[11] resets to zero and serves as a stop bit, until the capture event completes. Set GLOB_CMD[11] = 1 to stop a capture event that is in progress.
Table 18. ALM_CTRL Bit Descriptions
Bit [15:6] [5]
Automatic Capture Mode
In the automatic mode, the ADIS16220 executes capture events periodically, according to the time in CAPT_PRD (see Table 16). Table 17 provides an example for configuring and starting the automatic mode. When the device receives the start command, it executes a capture event, and then starts the countdown for executing the next capture event. Once the automatic mode starts, GLOB_CMD[11] becomes a stop bit. Table 16. CAPT_PRD Register Bit Descriptions
Bit [15:10] [9:8] Description (Default = 0x0000) Reserved Scale 00 = 1 second/LSB 01 = 1 minute/LSB 10 = 1 hour/LSB Data bits, binary format
[4] [3] [2] [1] [0]
Table 19. ALM_MAGA Bit Descriptions
Bit [15:0] Description (Default = 0x0000) Data bits for acceleration threshold setting; twos complement, 19.073 mg/LSB. Range = +8191 LSBs/-8192 LSBs.
[7:0]
Rev. 0 | Page 12 of 20
ADIS16220
Table 20. ALM_MAG1 and ALM_MAG2 Bit Descriptions
Bit [15:0] Description (Default = 0x0000) Data bits for AIN1, AIN2 signal threshold setting; twos complement, 305.18 V/LSB. Range = +8191 LSBs/-8192 LSBs.
Use the following equations to estimate capture times:
1 1024 2 AVG _ CNT (no flash) 97,184 1 TC 0.516 1024 2 AVG _ CNT (with flash) 97,184 TC 0.014 See Table 24 for the AVG_CNT setting.
Table 21. ALM_MAGS Bit Descriptions
Bit [15:12] [11:0] Description (Default = 0x0000) Reserved. Data bits for temperature or supply threshold setting. Binary format matches CAPT_TEMP or CAPT_SUPPLY format, depending on the ALM_CTRL[4] setting.
GLOBAL COMMANDS
The GLOB_CMD register provides an array of single-write commands for convenience. Setting the assigned bit in Table 23 to 1 activates each function. When the function completes, the bit restores itself to 0. For example, clear the capture buffers using a single DIN write sequence, DIN = 0xBF01. All of the commands in the GLOB_CMD register require the power supply to be within normal limits for the execution times listed in Table 23. The execution times reflect the factory default configuration where applicable and describe the time required to return to normal operation.
Table 23. GLOB_CMD Bit Descriptions
Bit [15:14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0]
1
Each ALM_MAGx register has a corresponding error flag in the DIAG_STAT register for software monitoring of alarm conditions. Note that the system alarm in the ALM_MAGS register (see Table 21) has an error flag in DIAG_STAT[11] but cannot trigger a data capture. Table 22. Example Event Mode Configuration Sequence
DIN 0xA00C, 0xA102 0xA809 Description Set acceleration trigger point at >+10 g and <-10 g by setting ALM_MAGA = 0x020C. Set the system alarm as a greater-than-temperature configuration and enable both acceleration and system alarms by setting ALM_CTRL[7:0] = 0x09. Keep DIO1 as a busy indicator and set DIO2 as a positive alarm indicator by setting DIO_CTRL[7:0] = 0x1F. Set capture into event mode, enable automatic capture store to flash, enable power-down between captures, and set pre-event capture length to 128 samples by setting CAPT_CTRL[7:0] = 0x5A. Start the event capture mode by setting GLOB_CMD[11] = 1
0xB61F 0x9C5A
0xBF08
Power-Down Control
CAPT_CTRL[1] provides an option to automatically power down the device after a capture event to reduce power consumption. Wake the device from power-down by lowering CS. The timer in automatic mode can wake the device up as well. Allow for a 2 ms wake-up time after lowering CS to wake the device up. Communication with the device while in sleep mode wakes up the device. The device remains awake until after the next capture or until the device is manually put back to sleep. When data is extracted after a capture, the user can command the device to go back to sleep by setting GLOB_CMD[1] = 1 (DIN = 0xBE02). When waking multiple devices, CS must occur at different times to avoid conflicts on the DOUT line.
Description Reserved Restore capture data and settings from flash memory Copy capture data and settings to flash memory Capture mode start/stop Set CAPT_PNTR = 0x0000 Reserved Clear capture buffers Software reset Reserved Flash test, compare sum of flash memory with the sum of SRAM Clear DIAG_STAT register Factory setting restore Self-test Power-down, requires toggling CS low to wake up Autonull
Execution Time1 N/A 0.88 ms (no capture) 6.91 ms (with capture) 350 ms (no capture) 502 (with capture) N/A 0.037 ms N/A 0.84 ms 22.7 ms N/A 10.5 ms 0.035 ms 335 ms 12 ms N/A 678 ms
This indicates the typical duration of time between the command write and the device returning to normal operation.
FILTERING
The ADIS16220 provides an averaging/decimation filter for lower bandwidth applications that may value finer frequency resolution using the 1024-sample capture buffer.
MEMS SENSOR AVERAGING FILTER N POWER SUPPLY COMPENSATION TO CAPTURE MEMORY AND OUTPUT REGISTERS
07980-009
Automatic Flash Back-Up Control
CAPT_CTRL[6] provides an option for automatically storing capture buffer data to a mirror location in the nonvolatile flash memory at the end of a capture. When an alarm condition has been met, the device also performs a system backup, which stores the registers and capture buffers in flash memory. Set GLOB_CMD[13] = 1 (DIN = 0xBF40) to recover these settings from the flash memory.
ADC + /N
OFFSET NULL REGISTER
Figure 15. Simplified Signal Processing Flowchart
Rev. 0 | Page 13 of 20
ADIS16220
AVG_CNT[3:0] controls the averaging/decimating filter structure in binomial steps, starting with 1 and ending with 1024. For example, set AVG_CNT[7:0] = 0x08 (DIN = 0xB608) to select 256 averages and a decimation rate of 1/256. Note that the decrease in sample time impacts the total capture time (TC): AVG_CNT[7:0] = 0x08 = 8, N = 28 = 256 averages
Table 24. AVG_CNT Bit Descriptions
Bit [15:4] [3:0] Description (Default = 0x0000) Reserved Power-of-two setting for number of averages, binary [3:2]
Table 27. DIO_CTRL Bit Descriptions
Bit [15:6] [5:4] Description (Default = 0x000F) Reserved DIO2 function selection 00 = general-purpose I/O (use GPIO_CTRL) 01 = alarm indicator output (per ALM_CTRL) 10 = capture trigger inputs 11 = busy indicator output DIO1 function selection 00 = general-purpose I/O (use GPIO_CTRL) 01 = alarm indicator output (per ALM_CTRL) 10 = capture trigger inputs 11 = busy indicator output DIO2 line polarity; if [5:4] = 00, see GPIO_CTRL 1 = active high 0 = active low DIO1 line polarity; if [3:2] = 00, see GPIO_CTRL 1 = active high 0 = active low
OFFSET ADJUSTMENT
The ACCL_NULL, AIN1_NULL, and AIN2_NULL registers provide a bias adjustment function. For example, setting ACCL_NULL = 0x009D (DIN = 0x829D) increases the acceleration bias by 157 LSB (3 g). Set GLOB_CMD[0] = 1 (DIN = 0x3E01) to execute the autonull function, which loads the offset registers with a value derived from a 678 ms average of the acceleration data.
Table 25. ACCL_NULL Bit Descriptions
Bit [15:0] Description (Default = 0x0000) Data bits, twos complement, 19.073 mg/LSB sensitivity. See Figure 15 for impact on output. Range = +8191 LSBs/-8192 LSBs [1]
[0]
Table 28. GPIO_CTRL Bit Descriptions
Bit [15:10] [9] [8] [7:2] [1] [0] Description (Default = 0x0000) Reserved General-purpose I/O output level, DIO2 General-purpose I/O output level, DIO1 Reserved General-purpose I/O Line, data direction control, DIO2 1 = output, 0 = input General-purpose I/O Line, data direction control, DIO1 1 = output, 0 = input
Table 26. AIN1_NULL and AIN2_NULL Bit Descriptions
Bit [15:0] Description (Default = 0x0000) Data bits, twos complement, 305.18 V/LSB sensitivity. Signal path is similar to Figure 15. Range = +8191 LSBs/-8192 LSBs
INPUT/OUTPUT FUNCTIONS
DIO1 and DIO2 are configurable as I/O lines that serve multiple purposes. The following register priority governs their operation: DIO_CTRL, then GPIO_CTRL. The DIO_CTRL register has four application-specific configuration options for each signal. The capture trigger input option works in conjunction with the manual capture mode and provides a hardware option for driving a data capture event. When enabled, this function searches for a positive pulse and the capture starts on the falling edge of this pulse. The busy indicator output is active during capture events and can help prevent undesirable interruptions. For example, set DIO_CTRL[5:0] = 101111 (DIN = 0xB62F) to establish DIO2 as a capture trigger input and keep DIO1 as a positive polarity, busy indicator output. Using the busy indicator as an interrupt driver enables the master processor to gather capture data as soon as it is available, without having to poll inputs or estimate execution times. The alarm indicator output is active when the trigger set by ALM_CTRL and ALM_MAGx activates. When configured as general-purpose lines, the GPIO_CTRL register configures DIO1 and DIO2. For example, set GPIO_CTRL = 0x0103 (DIN = 0xB203, then 0xB301) to set DIO1 and DIO2 as outputs, with DIO1 in a 1 state and DIO2 in a 0 state.
DIAGNOSTICS
In all of the error flags in DIAG_STAT, a 1 identifies an error condition, whereas a 0 signals normal operation. All of the flags remain until the next capture or reset command (GLOB_CMD[4] = 1). DIAG_STAT[1:0] returns to 1 after the next sample (or capture) if the error conditions still exist. DIAG_STAT[14:12] provide flags to check the source of an event capture, prior to reading the entire capture buffer. DIAG_STAT[10:8] offers flags that check the peak values in the capture against the conditions in the ALM_CTRL and ALM_MAGx registers. The flash test produces an error flag in DIAG_STAT[6] to check if the sum of the internal operating memory matches the sum of the same flash memory locations. The capture period violation flag (DIAG_STAT[4]) rises to 1 when the user attempts to use the SPI while a capture sequence is in progress. Using the DIO1 line in the factory default configuration as a busy indicator can help prevent this violation. The SPI communication flag in DIAG_STAT[3] raises to a Logic 1 when the total number of SCLK clocks is not a multiple of 16 during a SPI transfer.
Rev. 0 | Page 14 of 20
ADIS16220
Table 29. DIAG_STAT Bit Descriptions
Bit [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] [0] Description (Default = 0x0000) Reserved AIN2 sample > ALM_MAG2 AIN1 sample > ALM_MAG1 Acceleration sample > ALM_MAGA Error condition programmed into ALM_MAGS[11:0] and ALM_CTRL[5:4] is true |Peak value in AIN2 data capture| > ALM_MAG2 |Peak value in AIN1 data capture| > ALM_MAG1 |Peak value in acceleration data capture| > ALM_MAGA Data ready, capture complete Flash test result, checksum flag Self-test diagnostic error flag Capture period violation/interruption SPI communications failure Flash update failure Power supply above 3.625 V Power supply below 3.15 V
MSC_CTRL[1:0] provides an option for reducing the sensitivity dependence on power supply for ratiometric sensors, such as the ADXL001.
Table 31. ST_DELTA Bit Descriptions
Bit [15:0] Description Acceleration data, twos complement, 19.073 mg/LSB
SERIALIZATION
LOT_ID1 and LOT_ID2 combine to provide a unique lot code that is 24 bits in length. SERIAL_NUM provides a unique serial number for each device within a given lot.
Table 32. LOT_ID1 Bit Descriptions
Bit [15:8] [7:0] Description Lot identification code, least significant byte Reserved for internal use, do not use
Table 33. LOT_ID2 Bit Descriptions
Bit [15:0] Description Lot identification code, most significant bytes
Self-Test
The internal MEMS sensing element has an electrostatic selftest function that simulates the physical displacement associated with an acceleration event. There are two options for using this feature to verify the integrity of the accelerometer sensor and signal chain. Set GLOB_CMD[2] = 1 to execute an automatic self-test sequence, which exercises the sensing element, observes the change in output, records it into ST_DELTA, compares it with preset minimum/maximum values, and reports the pass/fail result in DIAG_STAT[5]. Another option is to set MSC_CTRL[8] = 1 (see Table 30) to manually activate the sensing element. Then execute a manual capture, which reflects the response associated with the self-test setting.
Table 30. MSC_CTRL Bit Descriptions
Bit [15:9] [8] [7:2] [1] [0] Description (Default = 0x0003) Reserved Self-test enable, set to 1 to activate, (returns to 0 when complete) Reserved Power supply compensation, AIN2 1 = enable, 0 = disable Power supply compensation, AIN1 1 = enable, 0 = disable
Table 34. SERIAL_NUM Bit Descriptions
Bit [15:0] Description Serial number, lot-specific
FLASH MEMORY MANAGEMENT
The FLASH_CNT register (see Table 35) provides a tool for managing the flash memory's endurance. The FLASH_CNT register increments every time there is a write to the flash memory. Figure 16 quantifies the relationship between data retention and junction temperature.
Table 35. FLASH_CNT Bit Descriptions
Bit [15:0] Description Binary counter for writing to flash memory
600
RETENTION (Years)
450
300
150
07980-113
0
30
40
55
70
85
100
125
135
150
JUNCTION TEMPERATURE (C)
Figure 16. Flash/EE Memory Data Retention
Rev. 0 | Page 15 of 20
ADIS16220 APPLICATIONS INFORMATION
ASSEMBLY
When developing a process flow for installing ADIS16220 devices on PCBs, see the JEDEC standard document J-STD-020C for reflow temperature profile and processing information. The ADIS16220 can use the Sn-Pb eutectic process and the Pb-free eutectic process from this standard. See JEDEC J-STD-033 for moisture sensitivity level (MSL) handling requirements. The MSL rating for these devices is marked on the antistatic bags, which protect these devices from ESD during shipping and handling. Prior to assembly, review the process flow for information about introducing shock levels that exceed the absolute maximum ratings for the ADIS16220. PCB separation and ultrasonic cleaning processes can introduce high levels of shock and can damage the MEMS element. Bowing or flexing the PCB after solder reflow can also place large pealing stress on the pad structure and can damage the device. If this is unavoidable, consider using an underfill material to help distribute these forces across the bottom of the package. Tasca
INTERFACE BOARD
The ADIS16220/PCBZ provides the ADIS16220 function on a 1.2 inch x 1.3 inch printed circuit board (PCB), which simplifies the connection to an existing processor system. The four mounting holes accommodate either M2 (2mm) or Type 2-56 machine screws. These boards are made of IS410 material and are 0.063 inches thick. The second level assembly uses a SAC305-compatible solder composition (Pb-free), which has a presolder reflow thickness of approximately 0.005 inches. The pad pattern on the ADIS16220/PCBZ matches that shown in Figure 5. J1 and J2 are dual-row, 2 mm (pitch) connectors that work with a number of ribbon cable systems, including 3M Part Number 152212-0100-GB (ribbon-crimp connector) and 3M Part Number 3625/12 (ribbon cable).
J1/J2 PIN NUMBERS 1 3 5 7 9 11 2 4 6 8 10 12 J1 1 2 3 4 6 10 11 12 C1 7 8 5 9 16 9 1 4 2 3 13
ADIS16220CCCZ
RST SCLK CS DOUT DIN VDD GND AIN1 AIN2 DIO2 DIO1 NC NC NC NC VREF 14 12 6 5 7 10 8 11 15
J2 1 3 11 12 5 7 9 2 10 4 6 8
07980-016
GETTING STARTED QUICKLY
Once the ADIS16220 has a power supply voltage that reaches 3.15 V, it executes a start-up sequence that places the device in manual capture mode. The following code example initiates a manual data capture by setting GLOB_CMD[11] = 1 (DIN = 0xBF08) and reads all 1024 samples in the acceleration capture buffer, using DIN = 0x1400. The data from the first spi_reg_ read is not valid because this command is starting the process. The second spi_reg_read command (first read inside the embedded For loop) produces the first valid data. This code sequence produces CS, SCLK, and DIN signals similar to the ones found in Figure 12.
spi_write(BF08h); delay 30ms; Data(0) = spi_reg_read(14h); For n = 0 to 1023 Data(n) = spi_reg_read(14h); n = n + 1; end
Figure 17. Electrical Schematic
1.100
1.050 2 x 0.925 J1 2 x 0.673 U1
iSensor
J2
C1
4 x O0.087 M2x0.4
2 x 0.000 0.150
0.035 2 x 0.000
2 x 0.900
0.200
0.865
Figure 18. PCB Assembly View and Dimensions
Rev. 0 | Page 16 of 20
07980-017
ADIS16220 OUTLINE DIMENSIONS
9.35 9.20 SQ 9.05 2.6955 BSC (8x) 5.391 BSC (4x) PIN 1 INDICATOR 1.000 BSC (16x)
1
13 12
16
8.373 BSC (2x) 0.797 BSC (12x)
9 8 5 4
TOP VIEW
5.00 TYP
0.200 MIN (ALL SIDES)
BOTTOM VIEW
0.373 BSC (16x)
3.90 MAX
052609-C
SIDE VIEW
Figure 19. 16-Terminal Stacked Land Grid Array [LGA] (CC-16-2) Dimensions shown in millimeters
ORDERING GUIDE
Model1 ADIS16220CCCZ ADIS16220/PCBZ
1
Temperature Range -40C to +125C
Package Description 16-Terminal Stacked Land Grid Array [LGA] Evaluation Board
Package Option CC-16-2
Z = RoHS Compliant Part.
Rev. 0 | Page 17 of 20
ADIS16220 NOTES
Rev. 0 | Page 18 of 20
ADIS16220 NOTES
Rev. 0 | Page 19 of 20
ADIS16220 NOTES
(c)2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07980-0-12/09(0)
Rev. 0 | Page 20 of 20

▲Up To Search▲

Price & Availability of ADIS1622009

	To Download ADIS1622009 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .